YONG KYU LEE
Post Doctoral Fellow
Harris Group (Solid State &
Photonics Lab)
Department of Electrical Engineering
Tel: 650-723-7537 Fax:
650-723-4659
Room 311. CISX
Center for Integrated Systems
420 Via Palou, Stanford, CA 94305-4070
EDUCATION
l SEOUL NATIONAL UNIVERSITY, Seoul, KOREA (2001-2004) - Samsung Scholarship
Ph. D. in Electrical Engineering and Computer Science
l KOREA UNIVERSITY, Seoul, KOREA (1993-1995) - TA Scholarship
M.S. in Materials Science and Engineering, -
l KOREA UNIVERSITY, Seoul, KOREA (1989-1993) - SSanyong Scholarship
B.S. in Materials Science and Engineering -
TECHNICAL SKILLS
ü Professional Process Integration for Sub-100nm Logic & Flash Devices
ü Characterization of MOSFET & Flash Cells (with a MOS parameter analyzer)
ü Simulation with TSUPREM4, MEDICI, ATLAS
ü Expert Layout Capability for Devices, Circuit and Photo Mask (Cadence)
RESEARCH EXPERIENCE
l STANFORD UNIVERSITY, Solid State & Photonics Lab., at EE department (2004-Present), Stanford, USA
Ge/SiGe Material Based Application Devices for Electro-optics, MOSFET and Flash Memory
l SEOUL NATIONAL UNIVERSITY, Semiconductor Materials and Device Laboratory at EECS (2001-2004), Seoul, KOREA
2-Bit SONOS Flash Memory (2002-2004);
ü 0.09µm Physically-separated Twin-bit SONOS Memories by Inverted Sidewall Spacers, Self-aligned Nitride Memory Nodes
Vertical Channel Mult-level SONOS Flash Memory (2001-2002) ; Integration using 0.12µm Technology Node)
ü 0.12µm SONOS Flash Memory on SOI and Their Applications to Multi-level Operation
l SAMSUNG ELECTRONICS Co., Flash Embedded Logic Team , System LSI. (1995-2001), Kyungki-Do, KOREA
SuperFlash (SST FLASH) Devices (1999-2000) ; Integration using 0.35µm & 0.18µm Technology Node
ü 0.18µm Self-Aligned Split Gate Type Flash Memory Design, Fabrication and Analysis (2000)
ü 0.35µm Split Gate Type Flash Memory Development and Mass Production (1999).
EEPROM Embedded Logic Devices Node (1995-1998); Integration using 1.00µm & 0.50µm Technology
ü 0.50µm OTP (EPROM) Cell and Logic Design, Fabrication and Analysis and Mass Production (1998)
ü 0.85µm & 0.65µm EEPROM Embedded Logic (for Smart Card) Design, Fabrication and Analysis (1996-1997)
ü 1.00µm EEPROM Embedded Logic (for Smart Card) Fabrication and Analysis (1995)
PUBLICATIONS
JOURNAL PAPERS
1.Yong Kyu Lee, Jae Sung Sim, Suk Kang Sung, Chang Ju Lee, Tae Hun Kim, Jong Duk Lee, Byung Gook Park, Dong Hun Lee, and Young Wug Kim, "Multilevel Vertical-Channel SONOS Nonvolatile Memory on SOI," IEEE Electron Device Letters, Vol. 23, No. 11, pp. 664-666, Nov. 2002 (SCI)
2.Yong Kyu Lee, Ki Whan Song, Jae Woong Hyun, Jong Duk Lee, Byung Gook Park Sung Taeg Kang, Jeong Dong Choe, Sang Yeon Han, Jeong Nam Han, Sung Woo Lee, O Ik Kwon, Chilhee Chung, Donggun Park, and Kinam Kim, “Twin SONOS Memory with 30-nm Storage Nodes under a Merged Gate Fabricated with Inverted Sidewall and Damascene Process”, IEEE Electron Device Letters, Vol. 25, No. 5, pp. 317-319, May 2004 (SCI)
3.Yong Kyu Lee, Tae Hun Kim, Sang Hoon Lee, Jong Duk Lee and Byung-Gook Park, "Twin-Bit Silicon-Oxide-Nitride-Oxide-Silicon(SONOS) Memory by Inverted Sidewall Patterning (TSM-ISP)," IEEE Transactions on Nanotechnology, Vol. 2, Issue 4, pp. 246-252, Dec. 2003(SCIE)
4.Suk-Kang Sung, Il-Han Park, Chang Ju Lee, Yong Kyu Lee, Jong Duk Lee, Byung-Gook Park, Soo Doo Chae, Chung Woo Kim,” Fabrication and program/erase characteristics of 30-nm SONOS nonvolatile memory devices”, IEEE Transactions on Nanotechnology, Volume: 2 , Issue: 4 , Pages:258 – 264, Dec. 2003 (SCIE)
5.Suk-Kang Sung, Dae Hwan Kim, Jae-Sung Sim, Kyung Rok Kim, Yong Kyu Lee, Jong Duk Lee, Soo Doo Chae, Byung Man Kim, and Byung-Gook Park, "Single-Electron MOS Memory with a Defined Quantum Dot Based on Conventional VLSI Technology," Jpn. J. Appl. Phys. Vol. 41, Part 1, No. 4B, pp. 2606-2610, Apr. 2002 (SCI)
6.Yong Kyu Lee, Suk Kang Sung, Jae Seong Sim, Chang Ju Lee, Tae Hun Kim, Jong Duk Lee, Byung Gook Park, Dong Hun Lee and Young Wug Kim, "Multi-Level Vertical-Channel SONOS Nonvolatile Memory Using a Standard SOI Logic Process," Journal of the Korean Physical Society, Vol. 41, No. 6, pp. 908~911, Dec. 2002. (SCI)
7.Yong Kyu Lee, Jong Duk Lee and Byung-Gook Park, Sung Taeg Kang, Chilhee Chung, and Donggun Park,” Inverted Sidewall Spacer and Inner Offset Oxide Process for Excellent 2-bit SONOS Memory under 100-nm Gate Length”, Journal of Vacuum Science and Technology, Vol. 22, Issues 5, pp. 2493-2498, October 18. 2004 (SCI)
8. Yong Kyu Lee, Suk Kang Sung, Jae Sung Sim, Ki Whan Song, Jong Duk Lee, Byung-Gook Park, Sung Taeg Kang, Chilhee Chung, Donggun Park, Kinam Kim, "Scalable 2-bit silicon-oxide-nitride-oxide-silicon (SONOS) memory with physically separated local nitrides under a merged gate," Solid-State Electronics, Vol. 48, Issues 10-11, pp. 1771-1775, October-November 2004. (SCI)
9. Ki-Whan Song, Yong Kyu Lee, Jae Sung Sim, Kyung Rok Kim, Jong Duk Lee, Byung-Gook Park, Young Sub You, Joo-On Park, You Seung Jin and Young-Wug Kim, "Complementary Self-Biased Logics Based on Single-Electron Transistor (SET)/CMOS Hybrid Process," Jpn. J. Appl. Phys. Vol. 44, pp. 2618-2622, No. 4B, April 2005. (SCI)
10. Ki-Whan Song, Yong Kyu Lee, Jae Sung Sim, Hoon Jeoung, Jong Duk Lee, Byung-Gook Park, You Seung Jin, and Young-Wug Kim, "SET/CMOS Hybrid Process and Multiband Filtering Circuits," IEEE Transactions on Electron Devices, Vol. 52, No. 8, pp. 1845-1850, August 2005. (SCI)
11. Yu-Hsuan Kuo, Yong Kyu Lee, Yangsi Ge, Shen Ren, Jonathan E. Roth, Theodore I. Kamins, David A. B. Miller, James S. Harris, “Strong quantum-confined Stark effect in germanium quantum-well structures on silicon,” Nature 437, 1334-1336, 2005 . (SCI)
CONFERENCE PAPERS
1. Yong Kyu Lee, Suk Kang Sung, Jae Seong Sim, Chang Ju Lee, Tae Hun Kim, Sang Hun Lee, Jong Duk Lee, Byung Gook Park, Dong Hun Lee and Young Wuk Kim, "Multi-Level Vertical Channel SONOS Nonvolatile Memory on SOI", 2002 Symposium on VLSI Technology, Honolulu, Hawaii, U.S.A, pp. 208-209, June 11-13, 2002
2 .S. K. Sung, Y.K.Lee, J.S.Sim, J.D.Lee, S.K.Kim, S.T.Kang, J.U.Han, and B.-G.Park, "Multi-Layer SONOS with Direct Tunnel Oxide for High Speed and Long Retention Time”, IEEE 2002 Silicon Nanoelectronics Workshop, Honolulu, Hawaii, U.S.A, pp. 83-84, June 9-10, 2002
3.Yong Kyu Lee, Suk Kang Sung, Jae Seong Sim, Jong Duk Lee and Byung Gook Park, Dong Hun Lee, Hyuk Ju Ryu,Young Wuk Kim, "Vertical Channel SONOS Nonvolatile Memory with SOI Technology," The 9th Korean Conference on Semiconductors, Chunan, Korea, pp. 317-318, Feb. 21-22, 2002
4.Jae Sung Sim, Yong Kyu Lee, Jong Duk Lee, and Byung-Gook Park, "Observation of the Lateral Redistribution of Locally Trapped Charge in SONOS Memory Cells," International Semiconductor Technology Conference 2002, Abstract No. 41, Tokyo, Japan, September 12-14, 2002.
5 Chang Ju Lee, Suk-Kang Sung, Yong Kyu Lee, Kyung Rok Kim, Jae Seong Sim, Tae Hun Kim, Ji Hye Kong, Jong Duk Lee, and Byung-Gook Park, "70-nm-long and 30-nm-wide Channel SONOS Memory Fabricated on an SOI Wafer," The 10th Korean Conference on Semiconductors, Seoul, Korea, pp. 581-582, Feb. 27-28, 2003.
6.Yong Kyu Lee, Tae Hun Kim, Sang Hoon Lee, Jong Duk Lee, and Byung-Gook Park, "Twin-Bit Silicon-Oxide-Nitride-Oxide-Silicon(SONOS) Memory by Inverted Sidewall Patterning (TSM-ISP)”, IEEE 2003 Silicon Nanoelectronics Workshop, Kyoto, Japan, pp. 92-93, June 8-9, 2003.
7.Sung Hun Jin, Yong Kyu Lee, Cheon An Lee, Jin Wook Kim, Byung-Gook Park, and Jong Duk Lee, "A Nonvolatile Pentacene Organic Memory (PENTOM) with a Triple-layer Gate Insulator on a Flexible Substrate,” 61st Annual Device Research Conference, pp. 185-186, Salt Lake, Utah, USA, June. 23-25, 2003.
8.Chang Ju Lee, Suk-Kang Sung, Yong Kyu Lee, Kyung Rok Kim, Jae Seong Sim, Tae Hun Kim, Ji Hye Kong, Jong Duk Lee, and Byung-Gook Park, Soo doo Chae, and Chung woo Kim, "70-nm-long and 30-nm-wide Channel SONOS Memory Fabricated on an SOI Wafer," IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, California, U.S.A, pp. 69-70, Feb. 16-20, 2003
9.Yong Kyu Lee, Jae Sung Sim, Suk Kang Sung, Tae Hoon Kim, Jong Duk Lee, and Byung-Gook Park Sung Taeg Kang, Chilhee Chung, Donggun Park, and Kinam Kim, “Excellent 2-bit Silicon-Oxide-Nitride-Oxide-Silicon(SONOS) Memory (TSM) with a 90-nm Merged-Triple Gate”, International Semiconductor Device Research Symposium, Washington, D.C., USA, pp. 489-490 December 10-12, 2003
10.Yong Kyu Lee, Ki Whan Song, Il Han Park, Jong Duk Lee and Byung Gook Park, Sung Taeg Kang, Jeong Dong Choe, Sang Yeon Han, Jeong Nam Han, Sung Woo Lee, O Ik Kwon, Chilhee Chung, Donggun Park, and Kinam Kim, "30-nm Twin Silicon-Oxide-Nitride-Oxide-Silicon(SONOS) Memory (TSM) with Low Voltage (4.0 V) Operation and High Reliability," The 11th Korean Conference on Semiconductors, Seoul, Korea, vol. 2, pp. 201-202, Feb. 19-20, 2004.
12.Byung Yong Choi, Yong-Kyu Lee, Woo Young Choi, Il Han Park, Dong-Soo Woo, Jong Duk Lee, Byung-Gook Park, Chang-Woo Oh, Chilhee Chung, and Donggun Park,” Nano-scale MOSFETs with Programmable Virtual Source/Drain” 62nd Annual Device Research Conference, USA, June. 21-23, 2004
13. Y. K. Lee, I. H. Park, J. S. Sim, J. D. Lee, B.-G. Park, S. T. Kang, C. Chung, D. Park, and K Kim, "Highly Scalable 2-bit SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) with 18 nm Storage Nodes under a Single Gate for Sub-90 nm Flash Technology," IEEE Non-Volatile Semiconductor Memory Workshop (20th NVSM Workshop), pp.96-97, Monterey, California, U.S.A., August 22-26, 2004
14.Yong Kyu Lee, Byung Yong Choi, Jae Sung Sim, Ki Whan Song, Jong Duk Lee and Byung-Gook Park ,Donggun Park, Chilhee Chung, ” A Highly Scalable Split-Gate SONOS Flash Memory with Programmable-Pass and Pure-Select Transistors for Sub-90-nm Technology, ” Int'l Conf. on Solid State Devices and Materials 2004, Tokyo, Japan, pp. 252-253, September 15-17 2004.
15. K.-W. Song, Y.K. Lee, K.R. Kim, J.I. Huh, J.D. Lee, B.-G. Park, J. Han, and Y.-W. Kim,”SET/CMOS Hybrid Integration Process for Multiple-Valued Logics,” Int'l Conf. on Solid State Devices and Materials 2004, Tokyo, Japan, pp. 122-123, September 15-17
16. Byung Yong Choi, Yong Kyu Lee, Woo Young Choi, Il Han Park, Hyungcheol Shin, Jong Duk Lee, Byung-Gook Park, Sung Taeg Kang, Chilhee Chung, and Donggun Park,”Programmable Virtual Source/Drain MOSFETs” 34th European Solid-State Device Research Conference, Leuven, Belgium, pp. 229-232, Sept. 20-24, 2004.
17 Chang Woo Oh; Kyoung Hwan Yeo; Min Sang Kim; Chang-Sub Lee; Dong Uk Choi; Sung Hwan Kim; Sung-Young Lee; Sung-Min Kim; Jung-Dong Choe; Yong Kyu Lee; Eun-Jung Yoon; Ming Li; Sung Dae Suk; Dong-Won Kim; Donggun Park; Kinam Kim,” Electrical characterization of partially insulated MOSFETs with buried insulators under source/drain regions” 34th European Solid-State Device Research Conference, Leuven, Belgium, pp. 233-236, Sept. 20-24, 2004.
18. Il Han Park, Yong Kyu Lee, Chang Ju Lee, Suk Kang Sung, Tae Hun Kim, Jae Sung Sim, Ji Hye Kong, Jong Duk Lee and Byung Gook Park,” Fabrication of 30 nm Square-Channel SONOS Flash Memory on SOI and Characterization of Program/Erase Operation in Nanoscale Regime” IEEE Non-Volatile Semiconductor Memory Workshop, Monterey, California, U.S.A, Aug. 22-26, 2004.
19. Chang Woo Oh, Sung Dae Suk, Yong Kyu Lee, Suk Kang Sung, Jung-Dong Choe, Sung-Young Lee, Dong Uk Choi, Kyoung Hwan Yeo, Min Sang Kim, Sung-Min Kim, Ming Li, Sung Hwan Kim, Eun-Jung Yoon, Dong-Won Kim, Donggun Park, and Kinam Kim,” Damascene Gate FinFET SONOS Memory Implemented on Bulk Silicon Wafer” IEEE IEDM, San Francisco, CA, December 13-15, 2004
20. Byung-Gook Park, Young Kyu Lee, Il Han Park, Chung Woo Kim, and Dong Gun Park, "Nanoscale SONOS Flash Memories," 2004 Asia-Pacific
Workshop on Fundamentals and Applications of Advanced Semiconductor Devices, Sasebo, Japan, pp. 179-184, June 30-July 2 2004.
21. Byung-Gook Park, Young Kyu Lee, Il Han Park, Chung Woo Kim, and Dong Gun Park, "Fabrication of Nanoscale Flash Memory Devices by Sidewall Spacer Patterning," U.S.-Korea Conference 2004, North Carolina, U.S,A., pp. 86, August 12-14 2004.
22. Byung-Gook Park, Yong Kyu Lee, Byung Yong Choi, and Dong Gun Park, "Nanoscale Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) Structure and Its Applications," 2004 7th International Conference on Solid-State and Integrated Circuits Technology Proceedings, Beijing, China, pp. 679-684, October 18-21, 2004
23. Byung Yong Choi, Byung-Gook Park, Yong Kyu Lee, Suk Kang Sung, Tae Yong Kim, Eun Suk Cho, Hye Jin Cho, Chang Woo Oh, Sung Hwan Kim, Dong Won Kim, Choong-Ho Lee, and Donggun Park, "Highly Scalable and Reliable 2-bit/cell SONOS Memory Transistor beyond 50nm NVM Technology Using Outer Sidewall Spacer Scheme with Damascene Gate Process," 2005 Symposium on VLSI Technology, Kyoto, Japan, pp. 118-119, June 14-16, 2005
24. Yu-Hsuan Kuo, Yong Kyu Lee, Shen Ren, Yangsi Ge, David A. B. Miller, and James S. Harris, “Quantum-Confined Stark Effect Electroabsorption in
Ge/SiGe Quantum Wells on Silicon Substrates,” IEEE LEOS (Lasers & Electro-Optics Society) 2005, Sydney Australiapp.284-285, Oct. 23-27, 2005
REFERENCE
1. Prof. Byung-Gook Park, School of Electrical Engineering, Seoul National University, +82-2-880-7270 (phone), bgpark@snu.ac.kr
(e-mail)
2. Associate Prof. Hyungcheol Shin, School of Electrical Engineering, Seoul National University, +82-2-880-1747 (phone), hcshin@snu.ac.kr (e-mail)
3. Prof. Jong Duk Lee, School of Electrical Engineering, Seoul National University, +82-2-880-7268 (phone), jdlee@snu.ac.kr (e-mail)
4. Prof. James S. Harris, Departement of Electrical Engineering, Stanford University, (650)-723-9775(phone), harris@snowmass.stanford.edu (e-mail)
Last updated on 11/11/2005/